The present invention relates to a static random access memory (SRAM).
SRAM devices have recently tended to have larger capacities thereby raising problems with a reduction of their power consumption and a cut-back on their access time. Thus, an attempt to achieve a shorter access time tends to accompany a larger power consumption. Since an increase in the consumed current results in the evolution of heat, and a deterioration in characteristics, etc., to restrain such an increase has been taken up as a theme in the way of improvement of the reliability of the element characteristics.
One of the major causes of the current which a SRAM consumes while it is in operation is the operation current required for precharging the bit lines. In an internally synchronized SRAM which operates upon the detection of a change in the address input, its read-out operation produces a precharge pulse which will bring a pair of bit lines to an equal electrical potential (e.g., 5 V) upon the detection of the change in the address input. At this time, one of the pair of bit lines is at a high level (e.g., 5 V), while the other is at a low level (e.g., 0 V). Then, by the use of the precharge pulse, the low level bit line is charged to be at an equipotential with the high level bit line. Subsequently, a memory cell connected to a word line corresponding to a selected address is selected, so that the data in the memory cell is delivered to the bit line. An electrical potential difference is thereby produced in such a manner that the electrical potential of the bit line corresponds to the data of the memory cell. When an electrical potential difference between the bit lines rises so as to be large enough to cause a sense amplifier to normally operate, the sense amplifier is operated in such manner that one of the bit lines is set at a high level, and the other is set at a low level. The data of the memory cell selected is delivered to the input and output terminals through the sense amplifier, whereby the read operation is performed.
Since in the read cycle, one of the bit lines is precharged from 0 V to 5 V and is again brought down to 0 V, the bit line will a repeat charge--discharge operation every time that the address input undergoes a change. For this reason, this system has a problem in that the consumed current increases as the memory capacity increases. (See, IEEE Vol SC-17, No. 5, pp804-pp809, October, 1982.)